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REV. 0
AD5532
TIMING CHARACTERISTICS
PARALLEL INTERFACE
–4–
Limit at T
MIN
, T
MAX
(A Version)
Parameter
1, 2
Unit
Conditions/Comments
t
1
t
2
t
3
t
4
t
5
t
6
0
0
50
50
20
0
ns min
ns min
ns min
ns min
ns min
ns min
CS
to
WR
Setup Time
CS
to
WR
Hold Time
CS
Pulsewidth Low
WR
Pulsewidth Low
A4–A0, CAL, OFFS_SEL to
WR
Setup Time
A4–A0, CAL, OFFS_SEL to
WR
Hold Time
NOTES
1
See Interface Timing Diagram.
2
Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
SERIAL INTERFACE
Limit at T
MIN
, T
MAX
(A Version)
Parameter
1, 2
f
CLKIN3
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
84
t
94
t
10
t
11
Unit
Conditions/Comments
14
28
28
10
50
10
5
5
20
60
400
400
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
SCLK Frequency
SCLK High Pulsewidth
SCLK Low Pulsewidth
SYNC
Falling Edge to SCLK Falling Edge Setup Time
SYNC
Low Time
D
IN
Setup Time
D
IN
Hold Time
SYNC
Falling Edge to SCLK Rising Edge Setup Time
SCLK Rising Edge to D
OUT
Valid
SCLK Falling Edge to D
OUT
High Impedance
10th SCLK Falling Edge to
SYNC
Falling Edge for Readback
24th SCLK Falling Edge to
SYNC
Falling Edge for DAC Mode Write
NOTES
1
See Serial Interface Timing Diagrams.
2
Guaranteed by design and characterization, not production tested.
3
In SHA mode the maximum SCLK frequency is 20 MHz and the minimum pulsewidth is 20 ns.
4
These numbers are measured with the load circuit of Figure 2.
Specifications subject to change without notice.
PARALLEL INTERFACE TIMING DIAGRAMS
CS
WR
A4
–
A0, CAL,
OFFS SEL
Figure 1. Parallel Write (SHA Mode Only)
I
OL
200 A
I
OH
200 A
C
50pF
TO
OUTPUT
PIN
1.6V
Figure 2. Load Circuit for D
OUT
Timing Specifications
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